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Floor plan tester for integrated circuit designпатент
- Авторы: Gasanov E.E., Zolotykh A.A., Pavisic I., Lu A.
- Номер: US 6,701,493
- Дата публикации патента: 2 марта 2004 г.
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Реферат (описание изобретения):
A method of testing a floor plan for an integrated circuit prior to resynthesis includes attempting to construct a least-penalty path connecting pins of each long distance pin pair in the floor plan to determine whether the floor plan has an unreachable pin; and if the least-penalty path is constructed, then attempting to construct a least-penalty path connecting pins of each long distance pin pair in the floor plan to determine whether the floor plan has a bottleneck.
- Добавил в систему: Гасанов Эльяр Эльдарович